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PCF8534
Universal LCD driver for low multiplex rates
Rev. 00.05 -- 20 February 2007 Preliminary datasheet
1. General description
The PCF8534 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 60 segments and can easily be cascaded for larger LCD applications. The PCF8534 is compatible with most microprocessors / microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized using a display RAM with auto-incremented addressing, hardware subaddressing and display memory switching (static and duplex drive modes).
2. Features
Single-chip LCD controller / driver Selectable backplane drive configuration: static or 2 / 3 / 4 backplane multiplexing Internal LCD bias generation with voltage-follower buffers 60 x 4-bit RAM for display data storage
Selectable display bias configuration: static, 12 or 13 60 segment drives: up to thirty 8-segment numeric characters; up to sixteen 15-segment alphanumeric characters; or any graphics of up to 240 elements Auto-incremented display data loading across device subaddress boundaries Versatile blinking modes Wide power supply range: from 1.8 to 5.5 V
Low power consumption TTL/CMOS compatible May be cascaded for 2 LCD applications Manufactured in silicon gate CMOS process.
Display memory bank switching in static and duplex drive modes LCD and logic supplies may be separated Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 6.5 V for guest-host LCDs and high threshold (automobile) twisted nematic LCDs 400 kHz I2C-bus interface Compatible with 4-bit, 8-bit or 16-bit microprocessors/microcontrollers No external components
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PCF8534
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1. Ordering information Topside mark Package Name Description Version plastic, low profile, quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 Type number PCF8534H
PCF8534H LQFP80
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4. Block diagram
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Universal LCD driver for low multiplex rates
I2C -B U S C O N TR O L
PCF8534
Fig 1. PCF8534 block diagram
NXP Semiconductors
PCF8534
Universal LCD driver for low multiplex rates
5. Pinning information
5.1 Pinning
80 S30
79 S29
78 S28
77 S27
76 S26
75 S25
74 S24
73 S23
72 S22
71 S21
70 S20
69 S19
68 S18
67 S17
66 S16
65 S15
64 S14
63 S13
62 S12
61 S11 60 59 58 57 56 55 54 53 52
S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 SDA 38 39 40
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 VLCD VSS SA0 A2 A1 A0 OSC SYNC VDD
PCF8534
51 50 49 48 47 46 45 44 43 42 41
SCL
CLK
MDB073v02
BP0
BP1
BP2
BP3
S51
S52
S53
S54
S55
S56
S57
S58
S59
n.c.
n.c.
n.c.
Fig 2. PCF8534 pin configuration Table 2. Pin 1 2 3 4 5 6 7 8 9
PCF8534_0
Pin allocation table Symbol S31 S32 S33 S34 S35 S36 S37 S38 S39 Pin 41 42 43 44 45 46 47 48 49 Symbol VDD SYNC OSC A0 A1 A2 SA0 VSS VLCD
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PCF8534
Universal LCD driver for low multiplex rates
Pin allocation table ...continued Symbol S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 BP0 BP1 BP2 BP3 n.c. n.c. n.c. n.c. SDA SCL CLK Pin 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30
Table 2. Pin 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
5.2 Pin description
Table 3. Symbol SDA SCL CLK VDD SYNC Pin description Pin 38 39 40 41 42 Description I2C-bus serial data input / output I2C-bus serial clock input external clock input / output supply voltage cascade synchronization input / output
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PCF8534
Universal LCD driver for low multiplex rates
Pin description Pin 43 44 to 46 47 48 49 30 to 33 Description internal oscillator enable input subaddress inputs I2C-bus slave address input: [0] logic ground LCD supply voltage LCD backplane outputs
Table 3. Symbol OSC
A0, A1 and A2 SA0 VSS VLCD BP0, BP1, BP2 and BP3 S0 to S59
50 to 80 LCD segment outputs and 1 to 29
6. Functional description
The PCF8534 is a versatile peripheral device designed to interface any microprocessor/microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 60 segments. The display configurations possible with the PCF8534 depend on the number of active backplane outputs required; a selection of display configurations is given in Table 4. All of the display configurations given in Table 4 can be implemented in the typical system shown in Figure 3. The host microprocessor / microcontroller maintains the 2-line I2C-bus communication channel with the PCF8534. The internal oscillator is selected by connecting pad OSC to VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are the power supplies (VDD, VSS and VLCD) and the LCD panel selected for the application.
Table 4. Number of Backplanes 4 3 2 1 Segments 240 180 120 60 Selection of display configurations 7 segment numeric Digits 30 22 15 7 Indicator symbols 30 26 15 11 14 segment numeric Characters 16 12 8 4 Indicator symbols 16 12 8 4 240 (4 x 60) 180 (3 x 60) 120 (2 x 60) 60 (1 x 60) Dot matrix
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PCF8534
Universal LCD driver for low multiplex rates
VDD R tr 2CB SDA SCL OSC VDD
VLCD
60 segment drives
HOST MICROPROCESSOR/ MICROCONTROLLER
LCD PANEL (up to 240 elements)
PCF8534
4 backplanes
A0 VSS
A1
A2
SA0 VSS
MGL744v02
Fig 3. Typical system configuration
6.1 Power-on-reset
At power on the PCF8534 resets to a starting condition as follows: 1. All backplane outputs are set to VLCD. 2. All segment outputs are set to VLCD. 3. The drive mode `1 : 4 multiplex with 13 bias' is selected. 4. Blinking is switched off. 5. Input and output bank selectors are reset (as defined in Table 7 old datasheet). 6. The I2C-bus interface is initialized. 7. The data pointer and the subaddress counter are cleared. 8. Display disabled. You must avoid data transfers on the I2C-bus for 1 ms following power on to allow the reset action to complete.
6.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of the three series resistors connected between VLCD and VSS. The centre resistor can be switched out of the circuit to provide a 12 bias voltage level for the 1:2 multiplex configuration.
6.3 LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by MODE SET commands from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VOP and the resulting discrimination ratios (D), are shown in Table 5.
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Universal LCD driver for low multiplex rates
A practical value for VOP is determined by equating VOFF(rms) with a defined LCD threshold voltage (VTH), typically when the LCD exhibits approximately 10% contrast. In the static drive mode a suitable choice is VOP > 3VTH. Multiplex drive ratios of 1:3 and 1:4 with 12 bias are possible but the discrimination and hence the contrast ratios are smaller e.g.: 21 3 = 1.732 for 1:3 multiplex or --------- = 1.528 for 1:4 multiplex 3 The advantage of these modes is a reduction of the LCD full-scale voltage VOP as follows:
* 1:3 multiplex (12 bias): V OP = 6 x V OFF ( rms ) = 2.449V OFF ( rms )
-------------------* 1:4 multiplex (12 bias): V OP = ( 4 x 3 ) = 2.309V OFF ( rms ) 3 These compare with VOP = 3 x VOFF(rms) when 13 bias is used. Note: VOP = VLCD.
Table 5. LCD drive mode static 1:2 1:2 1:3 1:4 Preferred LCD drive modes: summary of characteristics Number of: Backplanes 1 2 2 3 4 Levels 2 3 4 4 4 static
1 1 1 1 2 3 3 3
LCD bias configuration
V OFF ( ms ) ---------------------VOP 0 0.354 0.333 0.333 0.333
VON ( ms ) ------------------VOP 1 0.791 0.745 0.638 0.577
V ON ( ms ) D = ---------------------V OFF ( ms )
2.236 2.236 1.915 1.732
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Universal LCD driver for low multiplex rates
6.4 LCD drive mode waveforms
6.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 4.
Tframe VLCD BP0 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD state 1 (on) state 2 (off) LCD segments
state 1
0V
-VLCD VLCD
state 2
0V
-VLCD (b) Resultant waveforms at LCD segment.
mgl745
Vstate1(t) = Vsn(t) - VBP0(t). VON(rms) = VLCD. Vstate2(t) = V(sn + 1)(t) - VBP0(t). VOFF(rms) = 0 V.
Fig 4. Static drive mode waveforms
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PCF8534
Universal LCD driver for low multiplex rates
6.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8534 allows the use of 12 bias or 13 bias in this mode as shown in Figure 5 and Figure 6.
Tframe VLCD BP0 VLCD/2 VSS state 1 VLCD BP1 VLCD/2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V -VLCD/2 -VLCD VLCD VLCD/2 state 2 0V -VLCD/2 -VLCD (b) Resultant waveforms at LCD segment.
mgl746
LCD segments
state 2
Vstate1(t) = Vsn(t) - VBP0(t). VON(rms) = 0.791 VLCD. Vstate2(t) = V(sn)(t) - VBP1(t). VOFF(rms) = 0.354 VLCD.
Fig 5. Waveforms for the 1:2 multiplex drive mode with 12 bias.
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Universal LCD driver for low multiplex rates
Tframe VLCD BP0 2VLCD/3 VLCD/3 VSS VLCD BP1 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD Sn+1 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V -VLCD/3 -2VLCD/3 -VLCD (b) Resultant waveforms at LCD segment.
mgl747
LCD segments
state 1 state 2
Sn
Vstate1(t) = Vsn(t) - VBP0(t). VON(rms) = 0.745 VLCD. Vstate2(t) = V(sn)(t) - VBP1(t). VOFF(rms) = 0.333 VLCD.
Fig 6. Waveforms for the 1:2 multiplex drive mode with 13 bias.
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6.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 7.
Tframe VLCD BP0 2VLCD/3 VLCD/3 VSS VLCD BP1 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD Sn 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V -VLCD/3 -2VLCD/3 -VLCD state 1 state 2 LCD segments
BP2
Sn+1
Sn+2
(b) Resultant waveforms at LCD segment.
mgl748
Vstate1(t) = Vsn(t) - VBP0(t). VON(rms) = 0.638 VLCD. Vstate2(t) = V(sn)(t) - VBP1(t). VOFF(rms) = 0.333 VLCD.
Fig 7. Waveforms for the 1:3 multiplex drive mode.
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PCF8534
Universal LCD driver for low multiplex rates
6.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 8.
Tframe VLCD BP0 2VLCD/3 VLCD/3 VSS VLCD BP1 2VLCD/3 VLCD/3 VSS VLCD BP2 2VLCD/3 VLCD/3 VSS VLCD BP3 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD Sn+1 2VLCD/3 VLCD/3 VSS VLCD Sn+2 2VLCD/3 VLCD/3 VSS VLCD Sn+3 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V -VLCD/3 -2VLCD/3 -VLCD state 1 state 2 LCD segments
Sn
(b) Resultant waveforms at LCD segment.
mgl749
Vstate1(t) = Vsn(t) - VBP0(t). VON(rms) = 0.577 VLCD. Vstate2(t) = V(sn)(t) - VBP1(t). VOFF(rms) = 0.333 VLCD.
Fig 8. Waveforms for the 1:4 multiplex drive mode.
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PCF8534
Universal LCD driver for low multiplex rates
6.5 Oscillator
6.5.1 Internal clock
The internal logic and the LCD drive signals of the PCF8534 are timed either by the built-in oscillator or from an external clock. When the internal oscillator is used, you must connect pad OSC to VSS. In this event, the output from pad CLK provides the clock signal for cascaded PCF8534's in the system. After power-up, SDA must be HIGH to guarantee that the clock starts.
6.5.2 External clock
The condition for external clock is made by tying pad OSC to VDD; pad CLK then becomes the external clock input. The clock frequency (fCLK) determines the LCD frame frequency. A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state.
6.6 Timing
The timing of the PCF8534 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications the synchronization signal (SYNC) maintains the correct timing relationship between the PCF8534's in the system. The timing also generates the LCD frame frequency which it derives as an integer division of the clock frequency (see Table 6). The frame frequency is a fixed division of the internal clock or of the frequency applied to pad CLK when an external clock is used.
6.7 Display register
The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and one column of the display RAM.
6.8 Segment outputs
The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data resident in the display latch. When less than 60 segment outputs are required the unused segment outputs must be left open-circuit.
6.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required the unused outputs can be left open-circuit. In the 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements.
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6.10 Display RAM
The display RAM is a static 60 x 4-bit RAM which stores LCD data. A logic 1 in the RAM bit map indicates the on-state of the corresponding LCD segment; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the 60 segments operated with respect to backplane BP0 (see Figure 9). In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with BP1, BP2 and BP3 respectively. When display data is transmitted to the PCF8534 the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current mux mode data is stored singularly, in pairs, triplets or quadruplets. e.g. in 1:2 mux mode the RAM data is stored every second bit. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Figure 10; the RAM filling organization depicted applies equally to other LCD types. With reference to Figure 10, in the static drive mode the eight transmitted data bits are placed in bit 0 of eight successive display RAM addresses. In the 1:2 multiplex drive mode the eight transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses. In the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. In the 1:4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses.
Table 6. LCD frame frequencies Nominal frame frequency (Hz) 64
Frame frequency f CLK ---------24
Fig 9. Display RAM bit map showing direct relationship between backplane outputs, display RAM addresses and segment outputs, and between bits in a RAM word and backplane outputs.
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6.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the LOAD DATA POINTER command. Following this, an arriving data byte is stored starting at the display RAM address indicated by the data pointer thereby observing the filling order shown in Figure 10. The data pointer is automatically incremented in accordance with the chosen LCD configuration. That is, after each byte is stored, the contents of the data pointer are incremented by eight (static drive mode), by four (1:2 multiplex drive mode), by three (1:3 multiplex drive mode) or by two (1:4 multiplex drive mode). If an I2C-bus data access is terminated early then the state of the data pointer is unknown. The data pointer must be re-written prior to further RAM accesses.
6.12 Subaddress counter
The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the DEVICE SELECT command. If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF8534 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 27th display data byte transmitted in 1 : 3 multiplex mode). The hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface.
6.13 Output bank selector
The output bank selector selects one of the four bits per display RAM address for transfer to the display latch. The actual bit selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. In 1:4 multiplex, all RAM addresses of bit 0 are selected, these are followed by the contents of bit 1, bit 2 and then bit 3. Similarly in 1:3 multiplex, bits 0, 1 and 2 are selected sequentially. In 1:2 multiplex, bits 0 and 1 are selected and, in the static mode, bit 0 is selected. The SYNC signal will reset these sequences to the following starting points; bit 3 for 1:4 multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex and bit 0 for static mode. The PCF8534 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In the 1:2 drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled.
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6.14 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1:2 drive mode by using the BANK SELECT command. The input bank selector functions independently to the output bank selector.
6.15 Blinker
The display blinking capabilities of the PCF8534 are very versatile. The whole display can be blinked at frequencies selected by the BLINK command. The blinking frequencies are integer multiples of the clock frequency. The ratios between the clock and blinking frequencies depend on the mode in which the device is operating, see Table 7. An additional feature is for an arbitrary selection of LCD segments to be blinked. This applies to the static and 1:2 LCD drive modes and is implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specified by the BLINK command. In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can be effectively performed by resetting and setting the display enable bit E at the required rate using the MODE SET command.
Table 7. Blinking frequencies Normal operating mode ratio fCLK ---------768 f CLK ----------1536 f CLK ----------3072 Normal blinking frequency Blinking off 2 Hz 1 Hz 0.5 Hz
Blinking mode Off 2 Hz 1 Hz 0.5 Hz
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drive mode
LCD segments
a f g e d c b Sn+1 Sn Sn+7 DP
LCD backplanes
display RAM filling order
transmitted display byte
Sn+2 Sn+3 Sn+4
BP0
n bit/ BP 0 1 2 3 c x x x
n1 b x x x
n2 a x x x
n3 f x x x
n4 g x x x
n5 e x x x
n6 d x x x
n7 MSB DP x x x cbaf LSB g e d DP
static
Sn+5 Sn+6
Sn
BP0 a f g b
n bit/ BP
BP1 c
n1 f g x x
n2 e c x x
n3 d DP x x MSB abf LSB g e c d DP
1:2
Sn+1
multiplex
Sn+2 Sn+3
e d
DP
0 1 2 3
a b x x
Sn+1
a f g b Sn
BP0
n bit/ BP
c BP1 DP BP2
n1 a d g x
n2 f e x x MSB b DP c a d g f LSB e
1:3
Sn+2
multiplex
e d
0 1 2 3
b DP c x
Universal LCD driver for low multiplex rates
Sn
a f g b BP0 BP2
n bit/ BP
c BP1 DP BP3
n1 f e g d
1:4
multiplex
Sn+1
e d
0 1 2 3
a c b DP
MSB a c b DP f
LSB egd
mgl751
PCF8534
X = data bit unchanged
Fig 10. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C bus.
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7. Application design-in information
7.1 Characteristics of the I2C bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer is initiated only when the bus is not busy.
7.2 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Figure 11.
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 11. Bit transfer
7.3 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Figure 12.
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 12. Definition of START and STOP conditions
7.4 System configuration
A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'. The system configuration is illustrated in Figure 13.
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Preliminary datasheet
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PCF8534
Universal LCD driver for low multiplex rates
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
mga807
Fig 13. System configuration
7.5 Acknowledge
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 14.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 14. Acknowledgement of the I2C-bus
7.6 PCF8534 I2C-bus controller
The PCF8534 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8534 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress.
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In single device application, the hardware subaddress inputs A0, A1 and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress.
7.7 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.
7.8 I2C-bus protocol
Two I2C-bus slave addresses (01110000 and 01110010) are reserved for the PCF8534. The least significant bit of the slave address that a PCF8534 will respond to is defined by the level tied at its input SA0. The PCF8534 is a write only device and will not respond to a read access. Therefore, two types of PCF8534 can be distinguished on the same I2C-bus which allows: 1. Up to 16 PCF8534's on the same I2C-bus for very large LCD applications 2. The use of two types of LCD multiplex on the same I2C-bus. The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the two PCF8534 slave addresses available. All PCF8534's with the corresponding SA0 level acknowledge in parallel to the slave address, but all PCF8534's with the alternative SA0 level ignore the whole I2C-bus transfer. After acknowledgement, a control byte follows which defines if the next byte is RAM or command information. The control byte also defines if the next following byte is a control byte or further RAM/command data. In this way it is possible to configure the device then fill the display RAM with little overhead. The command bytes and control bytes are also acknowledged by all addressed PCF8534's connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data is directed to the intended PCF8534 device. The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCF8534. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be issued to RESTART an I2C-bus access.
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Preliminary datasheet Rev. 00.05 -- 20 February 2007
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NXP Semiconductors
R/W = 0 slave address control byte RAM/command byte M AS B L SP B S S 0 1 1 1 0 0 A 0 A Co RS 0
EXAMPLES a) transmit two bytes of RAM data S S011100A0A01 0 A RAM DATA A RAM DATA AP
b) transmit two command bytes S S011100A0A10 0 A COMMAND A00 A COMMAND AP
c) transmit one command byte and two RAM bytes S S011100A0A10 0 A COMMAND A01 A RAM DATA A RAM DATA AP
MGL752
Universal LCD driver for low multiplex rates
Fig 15. I2C-bus protocol
MSB Co RS UNUSED
LSB
MGL753
PCF8534
(1) C0 = 0; last control byte (2) C0 = 1; control bytes continue (3) RS = 0; data is a command byte (4) Rs = 1; data is a display byte
22 of 40
Fig 16. Control byte format
NXP Semiconductors
PCF8534
Universal LCD driver for low multiplex rates
7.9 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The five commands available to the PCF8534 are defined in Table 8.
Table 8. Command Mode set Definition of PCF8534 commands OPCODE 1 1 0 0 E B M1 M0 Options Table 9 Table 10 Table 11 Description defines LCD drive mode defines LCD bias configuration defines display status; the possibility to disable the display allows implementation of blinking under external control 7 bits of immediate data, bits P6 to P0, are transferred to the data pointer to define one of 8 hardware subaddresses 3 bits of immediate data, bits A0 to A3 are transferred to the subaddress counter to define one of 8 hardware subaddresses defines input bank selection (storage of arriving display data) defines output bank selection (retrieval of LCD display data); the BANK SELECT command has no effect in 1:3 or 1:4 multiplex drive modes defines the blinking frequency selects the blinking mode; normal operation with frequency set by BF1, BF0 or blinking by alteration of display RAM banks. Alteration blinking does not apply in 1:3 or 1:4 multiplex drive modes.
Load data pointer
0 P6 P5 P4 P3 P2 P1 P0
Table 12
Device select
1 1 1 0 0 A2 A1 A0
Table 13
Bank select
111110IO
Table 14 Table 15
Blink
1 1 1 1 0 A BF BF 10
Table 16 Table 17
Table 9.
Mode set option 1 Bits Backplane 1 BP MUX (2BP) MUX (3BP) MUX (4BP) Mode set option 2 Bit B 0 1 Mode set option 3 Bit E 0 1 M1 0 1 1 0 M0 1 0 1 0
LCD drive mode Drive mode static 1:2 1:3 1:4 Table 10. LCD bias
1 3 1 2
bias bias
Table 11.
Display status disabled (blank) enabled
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Universal LCD driver for low multiplex rates
Load data pointer option 1 Bits P6 P5 P4 P3 P2 P1 P0
Table 12.
Description 7 bit ordinary value of 0 to 59 Table 13. Device selected option 1
Description 3 bit binary value of 0 to 7 Table 14. Static RAM bit 0 RAM bit 2 Table 15. Static RAM bit 0 RAM bit 2 Table 16. Blink option 1 Bits BF1 off 2 Hz 1 Hz 1.5 Hz Table 17. Blink option 2 Bit A 0 1 0 0 1 1 Blank select option 1 (input) 1:2 MUX RAM bits 0 and 1 RAM bits 2 and 3 Blank select option 2 (output) 1:2 MUX RAM bits 0 and 1 RAM bits 2 and 3
Bits A2 A1 A0
Bit I 0 1
Bit O 0 1
Blink frequency
BF0 0 1 0 1
Blink mode normal blinking alteration blinking
[1]
[1]
Normal blinking is assumed when the multiplex rates 1:3 or 1:4 are selected.
7.10 Display controller
The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8534 and co-ordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order.
7.11 Cascaded operation
In large display configurations, up to 16 PCF8534's can be distinguished on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). When cascaded PCF8534's are synchronized they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of
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PCF8534
Universal LCD driver for low multiplex rates
only one device need to be through-plated to the backplane electrodes of the display. The other PCF8534's of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Figure 17). The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8534's. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments, or by the definition of a multiplex mode when PCF8534's with different SA0 levels are cascaded). SYNC is organized as an input / output pad; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCF8534 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is restored by the first PCF8534 to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCF8534 are shown in Figure 18. The contact resistance between the SYNC pads of cascaded devices must be controlled. If the resistance is too high then the device will not be able to synchronize properly. Table 18 shows the limiting values for contact resistance.
Table 18. 2 3 to 5 6 to 10 11 to 16 SYNC contact resistance Maximum contact resistance 6000 2200 1200 700
Number of devices
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handbook, full pagewidth
VDD SDA SCL SYNC CLK OSC A0 VLCD VDD tr 2CB SDA SCL SYNC CLK OSC A1
VLCD
60 segment drives
PCF8534
BP0 to BP3 (open-circuit)
LCD PANEL
A2
SA0 VSS
R
VDD
VLCD
60 segment drives
HOST MICROPROCESSOR/ MICROCONTROLLER
PCF8534
4 backplanes
BP0 to BP3
VSS
A0
A1
A2
SA0 VSS
MGL754v02
Fig 17. Cascaded PCF8534 configuration
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Universal LCD driver for low multiplex rates
1 Tframe = f frame
BP0
SYNC (a) static drive mode. BP1 (1/2 bias)
BP1 (1/3 bias)
SYNC (b) 1 : 2 multiplex drive mode.
BP2
SYNC (c) 1 : 3 multiplex drive mode.
BP3
SYNC
mgl755
(d) 1 : 4 multiplex drive mode.
Fig 18. Synchronization of the cascade for various PCF8534 drive modes
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8. Limiting values
Table 19. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IDD VLCD ILCD ISS VI(n) Parameter supply voltage supply current LCD supply voltage LCD supply current negative supply current input voltage on pads SDA, SCL, CLK, SYNC, SA0, OSC and A0 to A2 output voltage on pads s= to S59 and BP0 to BP3 DC input current DC output current total power dissipation power dissipation per output storage temperature Min -0.5 -50 VSS - 0.5 -50 -50 VSS - 0.5 Max +6.5 +50 +7.5 +50 +50 VDD + 0.5 Unit V mA V mA mA V
VO(n) II IO PTOT P / out TSTG
VSS - 0.5 -10 -10 -65
VLCD + 0.5 +10 +10 400 100 +150
V mA mA mW mW C
8.1 ESD values * ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 2000 V CDM per JESD22-C101.
* Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA.
9. Static characteristics
Table 20. Static characteristics VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; TAMB = -40 to +85C; unless otherwise specified Symbol Supplies VDD VLCD IDD ILCD Logic VIL VIH IOL1 Low-level input voltage High-level input voltage Low-level output current on pads CLK and SYNC VOL = 0.4 V; VDD = 5 V VSS 0.7 VDD 1 0.3 VDD VDD V V mA supply voltage LCD supply voltage supply current LCD supply current fCLK = 1536 Hz fCLK = 1536 Hz
[1] [1]
Parameter
Conditions
Min 1.8 2.5 -
Typ 8 24
Max 5.5 6.5 20 60
Unit V A A A
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Table 20. Static characteristics VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; TAMB = -40 to +85C; unless otherwise specified Symbol IOH1 IOL2 IL1 Parameter High-level output current pad CLK Low-level output current pad SDA leakage current pads SA0, A0 to A2, CLK, SDA and SCL leakage current pad OSC input capacitance power on reset voltage level DC voltage component on pads BP0 to BP3 DC voltage component on pads S0 to S59 output resistance at pads BP0 to BP3 output resistance at pads S0 to S59 CBP = 35 nF Conditions VOH = 4.6 V; VDD = 5 v VOL = 0.4 V; VDD = 5 V V1 = VDD or VSS Min -1 3 -1 Typ Max +1 Unit mA mA A
IL2 C1 VPOR
V1 = VDD
[2]
-1 1.0
1.3
+1 7 1.6
A pF V
LCD outputs VBP -100 +100 mV
VS
CS = 5 nF
-100
-
+100
mV
RBP RS
VLCD = 5 V VLCD = 5 V
[3]
-
1.5 6.0
10 13.5
k k
[3]
[1] [2] [3]
LCD outputs are open circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive. Not tested, design spec only. Outputs measured individually and sequentially.
10. Dynamic characteristics
Table 21. Dynamic characteristics VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; TAMB = -40 to +85C; unless otherwise specified Symbol fCLK(int) fCLK(ext) tCLKH tCLKL tr tf td(p)SYNC tSYNCL td(PLCD) fSCL tBUF
PCF8534_0
Parameter oscillator frequency on pad CLK (internal clock) oscillator frequency on pad CLK (external clock) input CLK HIGH time input CLK LOW time CLK rise time CLK fall time SYNC propagation delay time SYNC LOW time driver delays with test loads I2C bus SCL clock frequency bus free time between a stop and a start
Conditions VDD = 5 V VDD = 5 V
[1]
Min 960 797 130 130 1
Typ 1536 1536 30 -
Max 3046 3046 30 400 -
Unit Hz Hz s s ns ns ns s s kHz s
29 of 40
VLCD = 5 V
[2]
1.3
Timing characteristic:
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Preliminary datasheet
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NXP Semiconductors
PCF8534
Universal LCD driver for low multiplex rates
Table 21. Dynamic characteristics VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; TAMB = -40 to +85C; unless otherwise specified Symbol tHD;STA tSU;STA tLOW tHIGH tr tf Cb tSU;DAT tHD;DAT tSU;STO tSW
[1] [2]
Parameter start condition hold time set-up time for a repeated start condition SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time capacitive bus line load data set-up time data hold time set up time for stop condition tolerable spike width on bus
Conditions
Min 0.6 0.6 1.3 0.6 100 0 0.6 -
Typ -
Max 0.3 0.3 400 50
Unit s s s s s s pF ns ns s ns
Typical output duty cycle of 50%. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD.
gewidth
SYNC
6.8 (2%) 3.3 k (2%)
VDD
CLK
0.5VDD
SDA, SCL
1.5 k (2%)
VDD
BP0 to BP3, and S0 to S59
1 nF VSS
MGS120v02
Fig 19. Test loads
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1/ fCLK tCLKH tCLKL 0.7VDD 0.3VDD tr tf
CLK
SYNC
0.7VDD 0.3VDD td(p)(SYNC) tSYNCL 0.5 V td(p)(SYNC)
BP0 to BP3, and S0 to S59
(VDD = 5 V) 0.5 V tPLCD
MGL761v03
Fig 20. Driver timing waveforms
SDA
t BUF
t LOW
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA
t SU;STA t SU;STO
mga728
Fig 21. I2C-bus timing waveforms
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11. Package outline
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp pin 1 index 80 1 20 ZD bp D HD wM B vM B vM A 21 detail X Lp L A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.27 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1 Lp 0.75 0.30 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 o 0
o
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC 136E15 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 22. Package outline LQFP80
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12. Handling information
VDD SA0 VDD
handbook, full pagewidth
VSS VDD CLK
VSS
SCL VSS VDD VSS OSC
VSS VDD SYNC SDA
VSS VDD A0, A1 A2
VSS
VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD S0 to S59 VSS VLCD
VSS
MGL760v02
Fig 23. Device protection diagram
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13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 24) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 22 and 23
Table 22. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 23. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 24. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
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14. Revision history
Table 24. Revision history Release date tbd Data sheet status Preliminary Change notice Supersedes PCF8534_00.03 Document ID PCF8534_00.04 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 21: clock oscillator frequency (added external) Objective PCF8534_00.02 Table 1:added column for `Topside mark' Section 8.1: added ESD values. Objective Objective PCF8534_00.01 first release transfer to TDM format
PCF8534_00.03 Modifications: PCF8534_00.02 Modifications: PCF8534_00.01
20060829
* * *
20060725 20060628
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15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
PCF8534_0
(c) NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 -- 20 February 2007
38 of 40
NXP Semiconductors
PCF8534
Universal LCD driver for low multiplex rates
Notes
PCF8534_0
(c) NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 -- 20 February 2007
39 of 40
NXP Semiconductors
PCF8534
Universal LCD driver for low multiplex rates
17. Contents
1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 8 8.1 9 10 11 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Power-on-reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 7 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7 LCD drive mode waveforms . . . . . . . . . . . . . . . 9 Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 10 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 12 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 13 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Display register . . . . . . . . . . . . . . . . . . . . . . . . 14 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 14 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Subaddress counter . . . . . . . . . . . . . . . . . . . . 16 Output bank selector . . . . . . . . . . . . . . . . . . . 16 Input bank selector . . . . . . . . . . . . . . . . . . . . . 17 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application design-in information . . . . . . . . . 19 Characteristics of the I2C bus . . . . . . . . . . . . . 19 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 START and STOP conditions . . . . . . . . . . . . . 19 System configuration . . . . . . . . . . . . . . . . . . . 19 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20 PCF8534 I2C-bus controller . . . . . . . . . . . . . . 20 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 Command decoder . . . . . . . . . . . . . . . . . . . . . 23 Display controller . . . . . . . . . . . . . . . . . . . . . . 24 Cascaded operation . . . . . . . . . . . . . . . . . . . . 24 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28 ESD values . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Static characteristics. . . . . . . . . . . . . . . . . . . . 28 Dynamic characteristics . . . . . . . . . . . . . . . . . 29 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 32 12 13 13.1 13.2 13.3 13.4 14 15 15.1 15.2 15.3 15.4 16 17 Handling information . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 34 34 34 34 35 37 38 38 38 38 38 38 40
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 February 2007 Document identifier: PCF8534_0

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